datasheet pci-express gen1 clock source ICS557-01 idt? pci-express gen1 clock source 1 ICS557-01 rev p 072512 description the ICS557-01 is a clock chip designed for use in pci-express cards as a clock source. it provides a pair of differential outputs at 100 mhz in a small 8-pin soic package. using idt?s patented phase-locked loop (pll) techniques, the device takes a 25 mhz crystal input and produces hcsl (host clock signal level) differential outputs at 100 mhz clock frequency. lvds signal levels can also be supported via an alternative termination scheme. features ? supports pci-express tm hcsl outputs 0.7 v current mode differential pair ? supports lvds output levels ? packaged in 8-pin soic ? rohs 5 (green) or rohs 6 (green and lead free) compliant packaging ? operating voltage of 3.3 v ? low power consumption ? input frequency of 25 mhz ? short term jitter 100 ps (peak-to-peak) ? output enable via pin selection ? industrial temperature range available ? for pcie gen2 applications, see the 5v41064 ? for pcie gen3 applications, see the 5v41234 block diagram phase lock loop clock buffer/ crystal oscillator vdd gnd x2 25 mhz crystal /clock clk oe clk r r (iref) x1 crystal tuning capacitors
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 2 ICS557-01 rev p 072512 pin assignment pin descriptions 1 2 3 x1 4 x2 vdd iref gnd clk clk 8 7 6 5 oe 8 pin (150 mil) soic pin number pin name pin type pin description 1 oe input output enable signal (h = outputs are enabled, l = outputs are disabled/tristated). internal pull-up resistor. 2 x1 input crystal or clock input. connect to a 25 mhz crystal or single ended clock. 3 x2 xo crystal connection. connec t to a parallel mode crystal. leave floating if clock input. 4 gnd power connect to ground. 5 iref output a 475 precision resistor connected between this pin and ground establishes the external reference current. 6 clk output hcsl differential complementary clock output. 7 clk output hcsl differential clock output. 8 vdd power connect to +3.3 v.
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 3 ICS557-01 rev p 072512 applications information external components a minimum number of external components are required for proper operation. decoupling capacitors decoupling capacitors of 0.01 f should be connected between vdd and the ground plane (pin 4) as close to the vdd pin as possible. do not share ground vias between components. route power from power source through the capacitor pad and then into idt pin. crystal a 25 mhz fundamental mode parallel resonant crystal with c l = 16 pf should be used. this crystal must have less than 300 ppm of error across temperature in order for the ICS557-01 to meet pci express specifications. crystal capacitors crystal capacitors are connected from pins x1 to ground and x2 to ground to optimize the accuracy of the output frequency. c l = crystal?s load capacitance in pf crystal capacitors (pf) = (c l - 8) * 2 for example, for a crystal with a 16 pf load cap, each external crystal cap would be 16 pf. (16-8)*2=16. current source (iref) reference resistor - r r if board target trace impedance (z) is 50 , then r r = 475 (1%), providing iref of 2.32 ma. the output current (i oh ) is equal to 6*iref. output termination the pci-express differential clock outputs of the ICS557-01 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the ICS557-01can also be configured for lvds compatible voltage levels. see the lvds co mpatible layout guidelines section output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the ICS557-01.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 w
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 4 ICS557-01 rev p 072512 pci-express layout guidelines figure 1: pci-express device routing typical pci-express (hcsl) waveform common recommendations for differential routing dimension or value unit figure notes l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1,2 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1,2 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1,2 r s 33 ohm 1,2 r t 49.9 ohm 1,2 differential routing on a single pcb dimension or value unit figure notes l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 differential routing to a pci express connector dimension or value unit figure notes l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2 r s r s r t r t pci-express load or connector l1 l2 l3? l4 l1? l2? l3 l4? ICS557-01 output cloc k 0.175 v 0.52 v 0.175 v 0.52 v t or t of 500 ps 500 ps 700 mv 0
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 5 ICS557-01 rev p 072512 lvds compatible layout guidelines figure: lvds device routing typical lvds waveform vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 6 ICS557-01 rev p 072512 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ICS557-01. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. exposure to ab solute maximum rating conditions for extended periods can affect product reliability. electrical parameters are gua ranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c 1 single edge is monotonic when transitioning through region. 2 inputs with pull-ups/-downs are not included. item rating supply voltage, vdd, vdda 5.5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.465 input high voltage 1 v ih 2.0 vdd +0.3 v input low voltage 1 v il vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 a operating supply current i dd with 50 and 2 pf load 55 ma i ddoe oe =low 35 ma input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf pin inductance l pin 5nh output resistance rout clk outputs 3.0 k pull-up resistor r pup oe 60 k
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 7 ICS557-01 rev p 072512 ac electrical characteristics - clk/clk unless stated otherwise, vdd=3.3 v 5% , ambient temperature -40 to +85 c 1 test setup is r l =50 ohms with 2 pf, r r = 475 (1%). 2 measurement taken from a single-ended waveform. 3 measurement taken from a differential waveform. 4 measured at the crossing point where instantaneous voltages of both clkout and clkout are equal. 5 clkout pins are tri-stated when oe is low asserted. clkout is driven differential when oe is high. thermal characteristics (8-pin soic) parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency 100 mhz output high voltage 1,2 v oh 660 700 850 mv output low voltage 1,2 v ol -150 0 27 mv crossing point voltage 1,2 absolute 250 350 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 80 ps rise time 1,2 t or from 0.175 v to 0.525 v 175 332 700 ps fall time 1,2 t of from 0.525 v to 0.175 v 175 344 700 ps rise/fall time variation 1,2 125 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 30 s output disable time 5 all outputs 30 s stabilization time t stable from power-up vdd=3.3 v 3.0 ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 8 ICS557-01 rev p 072512 marking diagram (ics557m-01lf) marking diagram (ics557mi-01lf) notes: 1. ?lot? is the lot code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?l? or ?lf? designates pb (lead) free packaging. 4. ?i? denotes industrial temperature. 5. bottom marking: (origin). origin = country of origin if not usa. 4 85 557m01lf lot yyww 1 4 85 557mi01l lot yyww 1
ICS557-01 pci-express gen1 clock source pcie idt? pci-express gen1 clock source 9 ICS557-01 rev p 072512 package outline and packag e dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 557m-01lf see page 8 tubes 8-pin soic 0 to +70 c 557m-01lft tape and reel 8-pin soic 0 to +70 c 557mi-01lf tubes 8-pin soic -40 to +85 c 557mi-01lft tape and reel 8-pin soic -40 to +85 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 a0 8 0 8
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